module test_multidim2(
    input clk,
    input rst_n,
    // Multi-dimensional array port
    output [2:0][17:0] multi_dim_port,
    // Normal single-dimensional port
    output [7:0] normal_port,
    // Single bit port
    output single_bit_port
);

// Some instances
test_instance u_test (
    .clk(clk),
    .rst_n(rst_n),
    .data_out(multi_dim_port),
    .normal_out(normal_port),
    .single_out(single_bit_port)
);

endmodule

module test_instance(
    input clk,
    input rst_n,
    output [2:0][17:0] data_out,
    output [7:0] normal_out,
    output single_out
);

// Module implementation
endmodule